By Cicero S. Vaucher
This article describes a conceptual framework for interpreting the functionality of PLL frequency synthesizers, and provides optimization methods for different functionality elements. It includes uncomplicated details and in-depth wisdom, broadly illustrated with sensible layout examples utilized in business items.
Read or Download Architectures for RF Frequency Synthesizers (The Springer International Series in Engineering and Computer Science) PDF
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Extra resources for Architectures for RF Frequency Synthesizers (The Springer International Series in Engineering and Computer Science)
Robins, Phase Noise in Signal Sources, 9. , London, 2nd edition, 1996. L. Rohde, RF and Microwave Digital Frequency Synthesizers, Wiley, New York, 1997. F. Egan, “The Effect of Small Contaminating Signals in Nonlinear Elements Used in Frequency Synthesis and Conversion,” Proceedings of the IEEE, vol. 69, no. 7, pp. 797–811, July 1981. W. H. de Vreede, “Mixed-mode Telecom Design,” in Workshop on Advances in Analog Circuit Design (AACD), 2000, vol. 9. 1 INTRODUCTION This chapter gives an overview and analysis of single-loop PLL architectures; at the same time, equations and original insights are supplied in the text.
2 Frequency Dividers The digital frequency divider is responsible for frequency scaling within the loop. The frequency of the output signal equals the frequency of the 1 input signal divided by an integer number. The effect of the frequency division on the phase relationship between input and output signals is derived next. We will calculate the effect of frequency division on a signal which is phase modulated by a sine wave of frequency From this information we may derive a model for the frequency divider in the phase domain.
When the loop is locked the phase of the divided output signal accurately tracks the phase of the reference signal The phase-lock process forces the frequencies of and to be equal. 1 Voltage-Controlled Oscillators The voltage-controlled oscillator (VCO) generates the output signal of the PLL. The frequency of the VCO signal is dependent on the voltage at its tuning input. The relationship between the output frequency and the tuning voltage can be written as where is the VCO gain factor in [Hz/V] and is the output frequency when the tuning voltage is 0 Volt.